1. Field of the Invention
This invention relates to OR/AND field effect transistor (FET) circuits employing diodes in parallel configurations to perform the logic functions. In particular, the above logic circuits use Schottky diodes and a gallium arsenide (GaAs) substrate.
2. Related Art
FIG. 1 displays Schottky diode FET logic (SDFL) OR/AND invert logic circuit 10. Circuit 10 is published by Vu, et al in a Gallium Arsenide SDFL gate array with on chip RAM, IEEE Journal of Solid State Circuits, Vol. SC 19, No. 1, February 1984. The OR logic function is provided at logic node 14 for inputs A and B, and at logic node 12 for inputs C and D. Diode 16 and 18 provide current summing for inputs A and B as do diodes 20 and 22 for inputs C and D.
Node 24 tracks the voltage at node 12 except that diodes 26 and 27 shift the voltage level. Similarly, node 28 tracks the voltage at node 14 but the level is shifted by diode 30. FETs 31 and 32 serve as pull-down current sources to the respective logic branches.
The AND logic function is provided by the series connection of FETs 34 and 36, with INVERT provided at output node 38. FET 40 is a pull-up current source.
While circuit 10 provides a compact FET OR/NAND gate, it is limited in its fan-in and fan-out capabilities. In particular, the voltage swing between logic state 1 and logic state 0 is reduced relative to a single FET switching gate by the voltage drop across the additional FET 34 in series with FET 36. The smaller voltage swing reduces the noise margin and the fan-out of the circuit. The reduced noise margin also makes the circuit less radiation hard.